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MC9S08SH8 Datasheet, PDF (173/330 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.4 Functional Description
This section provides a complete functional description of the IIC module.
11.4.1 IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
⢠Start signal
⢠Slave address transmission
⢠Data transfer
⢠Stop signal
The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication
is described brieï¬y in the following sections and illustrated in Figure 11-9.
msb
lsb
SCL
1 2 34 5 6 78 9
msb
lsb
1 2 34 5 6 78 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX D7 D6 D5 D4 D3 D2 D1 D0
Start
Signal
Calling Address
Read/ Ack
Write Bit
msb
lsb
SCL
1 2 34 5 67 89
Data Byte
No Stop
Ack Signal
Bit
msb
lsb
1 234 5 678 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
Calling Address
Read/ Ack
Write Bit
Repeated
Start
Signal
New Calling Address
Figure 11-9. IIC Bus Transmission Signals
Read/ No Stop
Write
Ack Signal
Bit
11.4.1.1 Start Signal
When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a
master may initiate communication by sending a start signal. As shown in Figure 11-9, a start signal is
deï¬ned as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new
data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle
states.
MC9S08SH8 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
173
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