MC145170-2 Datasheet, PDF (17/32 Pages) Motorola, Inc – PLL Frequency Synthesizer with Serial Interface

Pin Connections
ENB
CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 ^*
MSB
LSB
D_in
N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
0 0 0 0 Not Allowed
0 0 0 1 Not Allowed
0 0 0 2 Not Allowed
0. 0. 0. 3. Not Allowed
.. ^{.. .. ..}
0 0 2 5 Not Allowed
0 0 2 6 Not Allowed
0 0 2 7 Not Allowed
0 0 2 8 N Counter = ÷40
0 0 2 9 N Counter = ÷41
0 0 2 A N Counter = ÷42
0. 0. 2. B. N Counter = ÷43
.. ^{.. .. ..}
F F F E N Counter = ÷65,534
F F F F N Counter = ÷65,535
Hexadecimal Value
Decimal Equivalent
* At this point, the two new bytes are transferred to the N register and stored. No other registers are affected. In addition, the N
and R counters are jam-loaded and begin counting down together.
Figure 18. N Register Access and Format (16 Clock Cycles Are Used)
Referencfe^R
OSC_in ÷ R
Feedbacfk^V
(f_in ÷ N
PD_out
V_H
V_L
V_H
V_L
*
V_H
High Impedance
V_L
φ_R
V_H
V_L
φ_V
V_H
V_L
LD
V_H
V_L
V_H = High voltage level
V_L = Low voltage level
*At this point, when both f_R and f_V are in phase, both the sinking and sourcing output FETs are turned on for a very short internal.
Note: The PD_out generates error pulses during out-of-lock conditions. When locked in phase and frequency, the output is high impedance
and the voltage at that pin is determined by the low-pass filter capacitor. PDout, φ_R and φ_V are shown with the polarity bit (POL) =
low; see Figure 16 for POL.
Figure 19. Phase/Frequency Detector and Lock Detector Output Waveforms
MC145170-2 Technical Data, Rev. 5
Freescale Semiconductor
17