56F8037_10 Datasheet, PDF (160/181 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Table 10-18 I²C Timing (Continued)
Characteristic
Standard Mode
Fast Mode
Symbol
Unit
Minimum Maximum Minimum Maximum
Set-up time for STOP
t_{SU; STO}
4.0
—
0.6
—
μs
condition
Bus free time between
t_BUF
4.7
—
1.3
—
μs
STOP and START
condition
Pulse width of spikes that
t_SP
N/A
N/A
0
must be suppressed by
50
ns
the input filter
1. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
2. The maximum t_{HD; DAT} must be met only if the device does not stretch the LOW period (t_LOW) of the SCL signal.
3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
4. A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement t_{SU; DAT} >= 250ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t_rmax + t_{SU; DAT} = 1000 + 250 = 1250ns (according to the Standard mode I²C bus specification) before the SCL line is
released.
5. C_b = total capacitance of the one bus line in pF
SDA
t_f
SCL
t_LOW
t_r
t_{SU; DAT}
t_f
t_{HD; STA}
t_SP
t_r
t_BUF
t_{HD; STA}
S
t_{HD; DAT}
t_HIGH
t_{SU; STA}
SR
t_{SU; STO}
P
S
Figure 10-15 Timing Definition for Fast and Standard Mode Devices on the I²C Bus
56F8037/56F8027 Data Sheet, Rev. 6
160
Freescale Semiconductor