56F8365_09 Datasheet, PDF (155/180 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Serial Peripheral Interface (SPI) Timing
SS
(Input)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
SS is held High on master
t_C
t_F
t_CL
t_CH
t_CL
t_CH
MSB in
t_R
Bits 14–1
t_R
t_F
t_DS
t_DH
LSB in
t_DV(ref)
t_DI
t_DV
t_DI(ref)
MOSI
(Output)
Master MSB out
Bits 14– 1
Master LSB out
t_F
t_R
Figure 10-11 SPI Master Timing (CPHA = 1)
56F8365 Technical Data, Rev. 8
Freescale Semiconductor
155
Preliminary