908E626 Datasheet, PDF (15/38 Pages) Freescale Semiconductor, Inc – Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication

FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
CURRENT LIMITATION FREQUENCY INPUT
TERMINAL (FGEN)
Input terminal for the half-bridge current limitation PWM
frequency. This input is not a real PWM input terminal; it
should just supply the period of the PWM. The duty cycle will
be generated automatically.
Important The recommended FGEN frequency should
be in the range of 0.1 kHz to 20 kHz.
BACK ELECTROMAGNETIC FORCE OUTPUT
TERMINAL (BEMF)
This terminal gives the user information about back
electromagnetic force (BEMF). This feature allows stall
detection and coil failures in step motor applications. In order
to evaluate this signal the terminal must be directly connected
to terminal PTD0 / TACH0 / BEMF.
RESET TERMINAL (RST_A)
RST_A is the bidirectional reset terminal of the analog die.
It is an open drain with pullup resistor and must be connected
to the RST terminal of the MCU.
INTERRUPT TERMINAL (IRQ_A)
IRQ_A is the interrupt output terminal of the analog die
indicating errors or wake-up events. It is an open drain with
pullup resistor and must be connected to the IRQ terminal of
the MCU.
SLAVE SELECT TERMINAL (SS)
This terminal is the SPI Slave Select terminal for the
analog chip. All other SPI connections are done internally. SS
must be connected to PTB1 or any other logic I/O of the
microcontroller.
LIN BUS TERMINAL (LIN)
The LIN terminal represents the single-wire bus
transmitter and receiver. It is suited for automotive bus
systems and is based on the LIN bus specification.
HALF-BRIDGE OUTPUT TERMINALS (HB1: HB4)
The 908E626 device includes power MOSFETs
configured as four half-bridge driver outputs. The HB1: HB4
outputs may be configured for step motor drivers, DC motor
drivers, or as high-side and low-side switches.
The HB1: HB4 outputs are short-circuit and
overtemperature protected, and they feature current recopy,
current limitation, and BEMF generation. Current limitation
and recopy are done on the low-side MOSFETs.
POWER SUPPLY TERMINALS (VSUP1: VSUP3)
VSUP1: VSUP3 are device power supply terminals. The
nominal input voltage is designed for operation from 12 V
systems. Owing to the low ON-resistance and current
requirements of the half-bridge driver outputs, multiple VSUP
terminals are provided.
All VSUP terminals must be connected to get full chip
functionality.
POWER GROUND TERMINALS (GND1 AND GND2)
GND1 and GND2 are device power ground connections.
Owing to the low ON-resistance and current requirements of
the half-bridge driver outputs multiple terminals are provided.
GND1 and GND2 terminals must be connected to get full
chip functionality.
SWITCHABLE V_DD OUTPUT TERMINAL (HVDD)
The HVDD terminal is a switchable V_DD output for driving
resistive loads requiring a regulated 5.0 V supply; The output
is short-circuit protected.
+ 5.0 V VOLTAGE REGULATOR OUTPUT
TERMINAL (VDD)
The VDD terminal is needed to place an external capacitor
to stabilize the regulated output voltage. The VDD terminal is
intended to supply the embedded microcontroller.
Important The VDD terminal should not be used to
supply other loads; use the HVDD terminal for this purpose.
The VDD, EVDD, VDDA, and VREFH terminals must be
connected together.
VOLTAGE REGULATOR GROUND TERMINAL
(VSS)
The VSS terminal is the ground terminal for the connection
of all non-power ground connections (microcontroller and
sensors).
Important VSS, EVSS, VSSA, and VREFL terminals
must be connected together.
LIN TRANSCEIVER OUTPUT TERMINAL (RXD)
This terminal is the output of LIN transceiver. The terminal
must be connected to the microcontroller’s Enhanced Serial
Communications Interface (ESCI) module (RXD terminal).
ADC REFERENCE TERMINALS (VREFL AND
VREFH)
VREFL and VREFH are the reference voltage terminals for
the ADC. It is recommended that a high-quality ceramic
decoupling capacitor be placed between these terminals.
Important VREFH is the high reference supply for the
ADC and should be tied to the same potential as VDDA via
separate traces. VREFL is the low reference supply for the
ADC and should be tied to the same potential as VSS via
separate traces.
For details refer to the 68HC908EY16 datasheet.
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E626
15