MC44BC375UA Datasheet, PDF (14/26 Pages) Freescale Semiconductor, Inc – PLL Tuned VHF Audio/Video High Integration IC

Modulator Functionality ^{Freescale Semiconductor, Inc.}
13 Modulator Functionality
13.1 Power Supply
The two device Vccs (pins 11 and 14) must be applied at the same time to ensure all internal blocks are
correctly biased. Do NOT bias any other pin before Vcc is applied to device.
13.2 Test Modes
The MC44BC375UA test modes are enabled by any voltage level higher than Vcc on pins CHS, PSS, SFS
and VIDEO. Care must be taken in the application to not reach levels higher than Vcc on those pins.
13.3 Standby Modes
During standby mode, the modulator is switched to low power consumption: the sound oscillator, UHF
oscillator and VHF dividers, video and sound modulator sections bias are internally turned OFF.
Modulator is programmed in standby mode when pin 9 PSave/LO is set to “LO” level (See PIN
SELECTION section).
13.4 Logic Output Port
The Logic Output Port is used to control an external switch (such as an antenna switch or an attenuator).
This pin is an open collector transistor able to drive up to 15mA at low voltage.
LOP level is switched between “HI” and “LO” level with pin 9 “Psave/LO” (See PIN SELECTION
section).
13.5 Transient Output Inhibit
To minimize the risk of interference to other channels while the UHF PLL is acquiring a lock on the
desired frequency, the Sound and Video modulators are turned OFF at power-ON from zero (i.e. Vcc is
switched from 0V to 5V or device is switched from “Standby mode” to “Normal operation”).
There is a time-out of 263ms until the output is enabled. This lets the UHF PLL settle to its programmed
frequency. During the 263ms time-out, the sound PLL current source is set to 10µA typical to speed up the
locking time; after the 263ms time-out, the current source is switched to 1 µA. Use care when selecting
loop filter components, to ensure the loop transient does not exceed this delay.
For test purposes, it is possible to disable the 263ms delay (see TEST MODES section).
13.6 Video Section
The modulator requires a composite video input with negative going sync pulses and a nominal level of
1Vp-p. This signal is AC coupled to the video input where the sync tip level is clamped.
Video modulation depth typical value is given for 1V_CBVS input level. It can be adjusted to any lower
value by simply adding a resistive divider at video input, resulting in a lower signal seen by the video input
stage.
MC44BC375UA Advance Information
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