IMX51AEC Datasheet, PDF (135/175 Pages) Freescale Semiconductor, Inc – i.MX51A Automotive and infotainment applications processors

Electrical Characteristics
Table 103. SSI Receiver Timing with Internal Clock (continued)
ID
Parameter
Min
Max
Unit
SS47
SS48
SS49
SS50
SS51
Oversampling Clock Operation
Oversampling clock period
Oversampling clock high period
Oversampling clock rise time
15.04
6.0
—
Oversampling clock low period
6.0
Oversampling clock fall time
—
—
ns
—
ns
3.0
ns
—
ns
3.0
ns
NOTE
• All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
• All timings are on Audiomux Pads when SSI is being used for data
transfer.
• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
• For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
135