S12TIM16B4CV1 Datasheet, PDF (13/32 Pages) Freescale Semiconductor, Inc – Four input capture/output compare channels

$_22
$_23
$_24 – $_2C
$_2D
$-2E – $_2F
Freescale Semiconductor_B, _lI_ocn_kc_G._{uide — S12TIM16B4CV1 V1.0}
Table 3-1 Module Memory Map
Pulse Accumulator Count Register
(PACNT(hi))
Pulse Accumulator Count Register
(PACNT(lo))
Reserved
Timer Test Register (TIMTST)
Reserved
Read/Write
Read/Write
Write has no effect
Read returns zero
Read/Write²
Write has no effect
Read retuns zero
NOTE: 1. Always read $00.
2. Only writable in special modes. (Refer to SOC Guide for different modes).
3. Write to these registers have no meaning or effect during input capture.
3.3 Register Descriptions
This section consists of register descriptions in address order.Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
3.3.1 Timer Input Capture/Output Compare Select (TIOS)
Register offset: $_00
Bit 7
6
5
4
3
2
R
0
0
W
IOS7
IOS6
IOS5
IOS4
RESET:
0
0
0
0
0
0
= Reserved
1
Bit 0
0
0
0
0
Read or write anytime.
IOS[7:4] — Input Capture or Output Compare Channel Configuration
1 = The corresponding channel acts as an output compare.
0 = The corresponding channel acts as an input capture.
3.3.2 Timer Compare Force Register (CFORC)
Register offset:$_01
Bit 7
6
5
4
3
2
1
Bit 0
R
0
0
0
0
0
0
0
0
W
FOC7
FOC6
FOC5
FOC4
RESET:
0
0
0
0
0
0
0
0
= Reserved
Read anytime but will always return $00. Write anytime.
13
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