56F8345 Datasheet, PDF (13/164 Pages) Motorola, Inc – 56F8345 16-bit Hybrid Controller

Architecture Block Diagram
5
JTAG / EOnCE
CHIP
TAP
Controller
pdb_m[15:0]
pab[20:0]
cdbw[31:0]
56800E
Boot
Flash
Program
Flash
Program
RAM
EMI*
11
Address
4
Data
6
Control
TAP
Linking
Module
xab1[23:0]
xab2[23:0]
Data RAM
External
JTAG Port
cdbr_m[31:0]
xdb2_m[15:0
Data
Flash
IPBus
Bridge
To Flash
Control
Logic
NOT available on the 56F8145 device.
* EMI not functional in this package; since only part of
the address/data bus is bonded out, use as GPIO pins
IPBus
Figure 1-1 System Bus Interfaces
Flash
Memory
Module
Note:
Note:
Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
13
Preliminary