MCIMX53XD Datasheet, PDF (122/204 Pages) Freescale Semiconductor, Inc – i.MX53xD Applications Processors for Consumer Products

Electrical Characteristics
Table 73. UDMA Out Burst Timing Parameters (continued)
ATA
Parameter
trfs1
—
tss
tmli
tli
tli
tli
tcvh
—
Parameter
from
Figure 73,
Figure 74,
Figure 75
trfs
tdzfs
tss
tdzfs_mli
tli1
tli2
tli3
tcvh
ton
toff
Value
trfs = 1.6 × T + tsui + tco + tbuf + tbuf
tdzfs = time_dzfs × T – (tskew1)
tss = time_ss × T – (tskew1 + tskew2)
tdzfs_mli =max (time_dzfs, time_mli) × T – (tskew1 + tskew2)
tli1 > 0
tli2 > 0
tli3 > 0
tcvh = (time_cvh ×T) – (tskew1 + tskew2)
ton = time_on × T – tskew1
toff = time_off × T – tskew1
Controlling
Variable
—
time_dzfs
time_ss
—
—
—
—
time_cvh
—
4.7.13 SATA PHY Parameters
This section describes SATA PHY electrical specifications.
4.7.13.1 Reference Clock Electrical and Jitter Specifications
The refclk signal is differential and supports frequencies of 25 MHz or 50-156.25 MHz (100 MHz and
125 MHz are common frequencies). The frequency is pin-selectable (for more information about the
signal, see “Per-Transceiver Control and Status Signals” in the SATA PHY chapter in the Reference
Manual).
Table 74 provides the SATA PHY reference clock specifications.
Table 74. Reference Clock Specifications
Parameters
Differential peak voltage (typically 0.71 V)
Common mode voltage
(refclk_p + refclk_m) / 2
Total phase jitter
Minimum/maximum duty cycle
Frequency range
Test Conditions
—
—
For information about total
phase jitter, see following
section
—
—
Min
Max
Unit
350
850
mV
175
2,000
mV
—
3
ps RMS
40
60
% UI
25
156.25
MHz
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