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MC68HC05B4_05 Datasheet, PDF (12/302 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Paragraph
Number
TABLE OF CONTENTS
7
PULSE LENGTH D/A CONVERTERS
Page
Number
7.1 Miscellaneous register....................................................................................... 7â3
7.2 PLM clock selection........................................................................................... 7â4
7.3 PLM during STOP mode ................................................................................... 7â4
7.4 PLM during WAIT mode .................................................................................... 7â4
8
ANALOG TO DIGITAL CONVERTER
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
8.5
A/D converter operation..................................................................................... 8â1
A/D registers...................................................................................................... 8â3
Port D data register (PORTD)...................................................................... 8â3
A/D result data register (ADDATA) ............................................................... 8â3
A/D status/control register (ADSTAT)........................................................... 8â4
A/D converter during STOP mode..................................................................... 8â6
A/D converter during WAIT mode...................................................................... 8â6
Port D analog input............................................................................................ 8â6
9
RESETS AND INTERRUPTS
9.1 Resets ............................................................................................................... 9â1
9.1.1 Power-on reset............................................................................................. 9â2
9.1.2
Miscellaneous register ................................................................................ 9â2
9.1.3 RESET pin ................................................................................................... 9â3
9.1.4 Computer operating properly (COP) watchdog reset .................................. 9â3
9.1.4.1
COP watchdog during STOP mode ....................................................... 9â4
9.1.4.2
COP watchdog during WAIT mode ........................................................ 9â4
9.1.5 Functions affected by reset.......................................................................... 9â5
9.2 Interrupts ........................................................................................................... 9â6
9.2.1 Interrupt priorities......................................................................................... 9â6
9.2.2 Nonmaskable software interrupt (SWI) ........................................................ 9â6
9.2.3 Maskable hardware interrupts ..................................................................... 9â7
9.2.3.1
External interrupt (IRQ).......................................................................... 9â7
9.2.3.2
Miscellaneous register .......................................................................... 9â9
9.2.3.3
Timer interrupts .................................................................................... 9â10
9.2.3.4
Serial communications interface (SCI) interrupts................................. 9â10
9.2.4 Hardware controlled interrupt sequence.................................................... 9â11
Freescale
iv
TABLE OF CONTENTS
MC68HC05B6
Rev. 4.1
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