MC143416 Datasheet, PDF (12/24 Pages) Freescale Semiconductor, Inc – Dual 16-Bit Linear Codec-Filter

Freescale Semiconductor, Inc.
DLOOP
ALOCAL LOOP
Tx0
AO+
INTERPOLATION
D/A
LPF
AND NOISE SHAPER
AO-
AI+
Rx0
SIGMA-DELTA
DECIMATION
MODULATOR
AAF
GAIN
AI-
ALOOP
Functional Path
Test Loops
Figure 4. Digital and Analog Loopback Features
CNTL0_1: Power Control Register — Codec 1
For Codec 1, refer to Power Control Register — Codec
0. The power control register address for Codec 1 is 0x1.
Pins AO0+, AO0–, AI0+, and AI0– for Codec 0 correspond to
pins AO1+, AO1–, AI1+, and AI1– for Codec 1, respectively.
CNTL1_0: Speaker Mixer Control and Other Analog
Control — Codec 0
HPF_EN (R/W, 0): This bit can be set to 1 when the codec
is processing voice data. It is used to perform an additional
high–pass filtering step on the voice D/A path to remove fre-
quencies below 0.005 * FS. (40 Hz @ 8 kHz, 60 Hz @
12 kHz, etc.)
IN_GAIN (1:0) (R/W, 0x0): These bits define a software
controlled gain on the input amplifier to the codec as defined
in Table 7.
Table 7. Input Signal Gain Control
IN_GAIN (1:0)
Signal Gain
00
0 dB
01
12 dB
10
24 dB
11
36 dB
SPK_Rx (1:0) and SPK_Tx (1:0) (R/W, 0x0): These regis-
ter bits provide control to the analog mixer. The mixer com-
bines four separate signal sources (AG0+, AO0+, AG1+, and
AO1+, which correspond to Rx0, Tx0, Rx1, and Tx1) and
provides a selection of four different amplification levels. The
combined and amplified signal is then fed into the speaker
driver. Two of these signal sources are from Codec 0 and the
other two are from Codec 1. The signal source from the out-
put amplifier is unaffected when the speaker driver amplifier
is turned off or by the settings of these control bits.
See the Speaker Driver and Mixer section for more de-
tail.
Each of the four channels (Rx0, Tx0, Rx1, and Tx1) can
provide one of the four attenuation levels to the signals that
source the analog mixer. Table 8 defines the levels for a giv-
en channel.
Table 8. Multiplexed Signal Gain Control
SPK_Rx (1:0),
SPK_Tx (1:0)
Gain
Rx
Tx
Effect on the Signal
Rx
Tx
00
0
0
Disconnected
01
1.5
0.5
3.5 dB
– 6 dB
10
3
1
9.5 dB
0 dB
11
6
2
15.6 dB + 6 dB
Note that it is possible to process more than one channel
at the same time; this feature provides some flexibility to the
user. Setting the amplification level of all the channels to zero
(0x0), has the effect of powering down the speaker driver/
multiplexer.
CNTL1_1: Speaker Mixer Control and Other Analog
Control — Codec 1
For Codec 1, refer to Speaker Mixer Control and Other
Analog Control — Codec 0. The speaker mixer control and
other analog control register address for Codec 1 is 0x3. Pins
AI0+, AI0–, AG0+, and AG0– for Codec 0 correspond to pins
AI1+, AI1–, AG1+, and AG1– for Codec 1, respectively.
CNTL2_0: OSR Clock Generation Control Register —
Codec 0
HSDIV (5:0) (R/W, 0x10): This field is used to program the
crystal frequency divide value that will determine the fre-
quency of the oversampling converters. The reset value of
this register is 0x10 (16 decimal).See Clock Generation for
a detailed description of the generation of clocks inside this
device.
MCLK0_SEL (WO, 0): When set to 0, the clock generation
block is sourced by the signal applied to XTALin. When set to
1, the source of the clocking for Codec 0 is defined to be
MCLK0.
CNTL2_1: OSR Clock Generation Control Register —
Codec 1
For Codec 1, refer to OSR Clock Generation Control
Register — Codec 0. The OSR clock generation control reg-
ister address for Codec 1 is 0x5. MCLK0 for Codec 0 corre-
sponds to MCLK1 for Codec 1.
MC143416
12
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