MC13224V_09 Datasheet, PDF (12/50 Pages) Freescale Semiconductor, Inc – Advanced ZigBee™- Compliant Platform-in-Package (PiP) for the 2.4 GHz IEEE® 802.15.4 Standard

2.7 IEEE 802.15.4 Acceleration Hardware
The MC13224V provides acceleration hardware for IEEE 802.15.4 applications and this hardware
includes 802.15.4 MAC acceleration and AES encryption/decryption.
2.7.1 802.15.4 MAC Accelerator (MACA) Overview
The MC13224V contains a hardware block that provides a low-level MAC and PHY link controller, which
together with software running on the ARM core, implements the baseband protocols and other low-level
link routine control and link control. Components of the MACA include a sequencer/controller (with
timers), TX and RX packet buffers, DMA block, frame check sequence (FCS) generator/checker, and
control registers. Figure 5 shows a MACA simplified block diagram.
As part of the 802.15.4 protocol, packets are generated and transmitted, packets are received and verified,
and channel energy is measured via a clear channel assessment (CCA). Also, combinations or sequences
of events are required as part of the protocol such as an ACK response following a received packet. The
MACA facilitates these activities via control of the transceiver and off loads the functions from the CPU.
A dedicated DMA function moves data between the MACA buffers and RAM on a cycle steal basis and
does not require intervention from the CPU.
The MACA is responsible for construction of packets for TX including FCS, and for parsing the received
packets. The MACA will also handle ACKs and TxPoll sequences independent of the ARM processor.
During TX the MACA will construct the entire packet. This includes preamble and SFD (start of frame
delimiter). During receive, the modem will recognize preamble and SFD, then the MACA will begin
receiving the packet with the first bit of frame length, and finally, will check the FCS.
Sequencer
Timers
Control
Registers
To
Transceiver
Modem
TX Packet
Buffer
RX Packet
Buffer
FCS Generator/
Checker
DMA
MACA
To
MCU
Bus
Figure 5. MAC Accelerator Simplified Block Diagram
NOTE
The radio can receive packets of either mode without prior indication of the
incoming packet mode.
MC13224V Technical Data, Rev. 1.2
12
Freescale Semiconductor