MC9S12XET256MAA Datasheet, PDF (119/1324 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

2.3.17 IRQ Control Register (IRQCR)
Chapter 2 Port Integration Module (S12XEPIMV1)
Address 0x001E
7
6
5
4
3
2
R
0
0
0
0
IRQE
IRQEN
W
Reset
0
1
0
0
0
0
= Unimplemented or Reserved
Figure 2-15. IRQ Control Register (IRQCR)
1. Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
Access: User read/write⁽¹⁾
1
0
0
0
0
0
Table 2-17. IRQCR Register Field Descriptions
Field
Description
7
IRQE
6
IRQEN
5-0
IRQ select edge sensitive only—
Special modes: Read or write anytime.
Normal & emulation modes: Read anytime, write once.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ configured for low level recognition.
External IRQ enable—
Read or write anytime.
1 External IRQ pin is connected to interrupt logic.
0 External IRQ pin is disconnected from interrupt logic.
Reserved—
2.3.18 PIM Reserved Register
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Address 0x001F
Access: User read⁽¹⁾
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1. Read: Always reads 0x00
Write: Unimplemented
Figure 2-16. PIM Reserved Register
NOTE
Writing to this register when in special modes can alter the pin functionality.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
119