68HC908MR24 Datasheet, PDF (118/406 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
5. Calculate the bus frequency, f_BUS, and compare f_BUS with
f_BUSDES.
f_BUS
=
f_VCLK
4
Example: N = ^{32 MHz} = 8 MHz
4 MHz
NOTE:
6. If the calculated f_BUS is not within the tolerance limits of your
application, select another f_BUSDES or another f_RCLK.
7. Using the value 4.9152 MHz for f_NOM, calculate the VCO linear
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
( ) L = round fVCLK
f_NOM
Example: L = ^{32 MHz}
4.9152 MHz
= 7 MHz
8. Calculate the VCO center-of-range frequency, f_VRS. The center-
or-range frequency is the midpoint between the minimum and
maximum frequencies attainable by the PLL.
f_VRS = L x f_NOM
Example: f_VRS = 7 x 4.9152 MHz = 34.4 MHz
For proper operation,
f_VRS – f_VCLK | ≤
f_NOM
2
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
Advance Information
118
Clock Generator Module (CGM)
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor