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56F8355 Datasheet, PDF (114/164 Pages) Freescale Semiconductor, Inc – 16-bit Hybrid Controllers | |||
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6.5.9.7 Quad Timer D Enable (TMRD)âBit 9
Each bit controls clocks to the indicated peripheral.
⢠1 = Clocks are enabled
⢠0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.8 Quad Timer C Enable (TMRC)âBit 8
Each bit controls clocks to the indicated peripheral.
⢠1 = Clocks are enabled
⢠0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.9 Quad Timer B Enable (TMRB)âBit 7
Each bit controls clocks to the indicated peripheral.
⢠1 = Clocks are enabled
⢠0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.10 Quad Timer A Enable (TMRA)âBit 6
Each bit controls clocks to the indicated peripheral.
⢠1 = Clocks are enabled
⢠0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.11 Serial Communications Interface 1 Enable (SCI1)âBit 5
Each bit controls clocks to the indicated peripheral.
⢠1 = Clocks are enabled
⢠0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12 Serial Communications Interface 0 Enable (SCI0)âBit 4
Each bit controls clocks to the indicated peripheral.
⢠1 = Clocks are enabled
⢠0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)âBit 3
Each bit controls clocks to the indicated peripheral.
⢠1 = Clocks are enabled
⢠0 = The clock is not provided to the peripheral (the peripheral is disabled)
56F8355 Technical Data, Rev. 5.0
114
Freescale Semiconductor
Preliminary
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