MCF547X_07 Datasheet, PDF (11/34 Pages) Freescale Semiconductor, Inc – MCF547x ColdFire® Microprocessor

6 PLL Timing Specifications
The specifications in Table 7 are for the CLKIN pin.
Table 7. Clock Timing Specifications
Num
Characteristic
Min
Max
C1 Cycle time
15.0
40
C2 Rise time (20% of Vdd to 80% of vdd)
—
2
C3 Fall time (80% of Vdd to 20% of Vdd)
—
2
C4 Duty cycle (at 50% of Vdd)
40
60
PLL Timing Specifications
Units
ns
ns
ns
%
C1
CLKIN
C4
C4
C2
C3
Figure 8. Input Clock Timing Diagram
Table 8 shows the supported PLL encodings.
Table 8. MCF547x Divide Ratio Encodings
AD[12:8]¹
Clock
Ratio
CLKIN—PCI and FlexBus
Frequency Range (MHz)
Internal XLB, SDRAM Bus,
and PSTCLK Frequency
Range (MHz)
Core Frequency Range
(MHz)
00011
1:2
00101
1:2
41.67–66.66
25.0–44.42
83.33–133.33
50.0–88.83²
166.66–266.66
100.0–177.66
01111
1:4
25.0–33.3
100–133.33
200–266.66
1 _{All other values of AD[12:8] are reserved.}
2 _{DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy down to 75 MHz. Check with the}
memory component specifications to verify.
Figure 9 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
CLKIN
Internal Clock
Core Clock
2x
25.0 66.66
50.0
2x
133.33
100.0
266.66
4x
25.0 33.33
25 50 70 30
CLKIN (MHz)
100.0
2x
133.33
200.0
266.66
50 70 90 110 130
60 80 100 120 140 160 180 200 220 240 260
Internal Clock (MHz)
Core Clock (MHz)
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios
MCF547x ColdFire^® Microprocessor, Rev. 4
Freescale Semiconductor
11