33937_09 Datasheet, PDF (11/48 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ V_PWR = V_SUP ≤ 40 V, -40°C ≤ T_A ≤ 135°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OVER-CURRENT COMPARATOR
Common Mode Input Range⁽²²⁾
Input Offset Voltage
Over-current Comparator Threshold Hysteresis⁽²¹⁾
Output Voltage
High Level at I_OH = -500 µA
Low Level at I_OL = 500 µA
V_CM
2.0
–
V_DD-0.02
V
V_{OS_OC}
-50
–
50
mV
V_{OC_HYST}
50
300
mV
V
V_OH
0.85 V_DD
–
V_DD
V_OL
–
–
0.5
HOLD OFF CIRCUIT
Hold Off Current (At Each GATE Pin)
3.0 V < V_SUP < 40 V⁽²³⁾
I_HOLD
10
–
300
µA
PHASE COMPARATOR
High Level Input Voltage Threshold
Low Level Input Voltage Threshold
High Level Output Voltage at I_OH = -500 µA
Low Level Output Voltage at I_OL = 500 µA
High Side Source Input Resistance^{(21), (26)}
DESATURATION DETECTOR
Desaturation Detector Threshold⁽²⁴⁾
CURRENT SENSE AMPLIFIER
V_{IH_TH}
V_{IL_TH}
V_OH
V_OL
R_IN
0.5 V_SUP
0.3 V_SUP
0.85 V_DD
–
–
V_{DES_TH}
1.2
–
0.65 V_SUP
V
–
0.45 V_SUP
V
–
V_DD
V
–
0.5
V
40
–
kΩ
1.4
1.6
V
Recommended External Series Resistor (See Figure 9)
Recommended External Feedback Resistor (See Figure 9)⁽²⁷⁾
Limited by the Output Voltage Dynamic Range
Maximum Input Differential Voltage (See Figure 9)
V_ID = V_{AMP_P} - V_{AMP_N}
Input Common Mode Range^{(21), (25)}
Input Offset Voltage
R_S = 1.0 kΩ, V_CM = 0.0 V
Input Offset Voltage Drift⁽²¹⁾
Input Bias Current
V_CM = 2.0 V
R_S
–
1.0
–
kΩ
R_FB
kΩ
5.0
–
15
V_ID
mV
-800
–
+800
V_CM
V_OS
-0.5
–
3.0
V
mV
-15
–
+15
δV_OS/δT
–
-10
–
µV/°C
I_b
nA
-200
–
+200
Notes
21. This parameter is a design characteristic, not production tested.
22. As long as one input is in the common mode range there is no phase inversion on the output.
23. The hold off circuit is designed to operate over the full operating range of V_SUP. The specification indicates the conditions used in
production test. Hold off is activated at V_THRST or V_THVLS.
24. Desaturation is measured as the voltage drop below V_SUP, thus the threshold is compared to the drain-source voltage of the external
High Side FET. See Figure 5.
25. As long as one input is within V_CM the output is guaranteed to have the correct phase. Exceeding the common mode rails on one input
will not cause a phase inversion on the output.
26. Input resistance is impedance from High Side source and is referenced to V_SS. Approximate tolerance is ±20%.
27. The current sense amplifier is unity gain stable with a phase margin of approximately 45°. See Figure 10.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33937
11