MC9S12XEG128MAL Datasheet, PDF (1027/1324 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
Address
& Name
7
6
5
4
3
2
1
0
= Unimplemented or Reserved
Figure 27-4. FTM512K3 Register Summary (continued)
27.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R FDIVLD
W
FDIV[6:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 27-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 27-8. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6–0
FDIV[6:0]
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 27-9 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 27.4.1, “Flash Command Operations,” for more information.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
Freescale Semiconductor
MC9S12XE-Family Reference Manual Rev. 1.25
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