P5010NXN1QMB Datasheet, PDF (1/2 Pages) Freescale Semiconductor, Inc – P5020/P5010 Processors

QorIQ Communications Platforms
QorIQ
P5020/P5010 Processors
Target Markets and Applications
The P5020 is designed for high-
performance, power-constrained control
plane applications and provides an
ideal combination of core performance,
integrated accelerators and advanced I/O
required for the following compute-intensive
applications:
• Enterprise equipment: Router, switch,
services
• Data center: Server appliance, SAN
storage controller, iSCSI controller,
FCoE bridging
• Aerospace and defense
• Industrial computing: Single-board
computers, test/measurement, robotics
Overview
The QorIQ P5 family delivers scalable 64-bit processing with single-, dual- and
quad-core devices. With frequencies scaling up to 2.0 GHz, a tightly coupled cache
hierarchy for low latency and integrated hardware acceleration, the P5020 (dual-core)
and P5010 (single-core) devices are ideally suited for compute intensive, power-
conscious control plane applications.
Q_Qoo_rIQrI_PQ₅₀P₂₀5_/P0₅₀2₁0₀ /_PP_ro5_ce0_ss1_o0_rs Processors
*Only Available on P5020
*Only Available on P5020
512 KB
Backside
L2 Cache
Power Architecture^®
e5500 Core
32 KB
D-Cache
32 KB
I-Cache
1024 KB
Frontside CoreNet
Platform Cache
1024 KB
Frontside CoreNet
Platform Cache
64-bit
DDR2/3
Memory Controller
64-bit
DDR2/3
Memory Controller
Security Fuse Processor
Security Monitor
2x USB 2.0
PAMU
eSDHC
eLBC
SD/MMC
Serial
RapidIO^{® Security}
Mgr.
4.0
Queue
Mgr.
2x DUART
2x I²C
SPI, GPIO
RAID
5/6
Engine
Pattern
Match
Engine
2.0
Buffer
Mgr.
PAMU
CoreNet Coherency Fabric
PAMU
PAMU
Peripheral Access
Management Unit
Frame Manager
Parse, Classify,
Distribute
1GE 1GE
10 GE 1GE
1GE 1GE
SATA SATA
2.0 2.0
RapidIO
Message
Unit
PCIe PCIe
2x DMA
Real-Time Debug
Watchpoint
Cross
Trigger
PCIe
SRIO
PCIe/
SRIO
Perf. CoreNet
Monitor Trace
Aurora
18-Lane 5 GHz SerDes
Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)
Accelerators and Memory Control
Networking Elements
Basic Peripherals and Interconnect
P5 Family Comparison Chart
CPU cores
Threads
Max core frequency
L2
L3/Platform
DDR I/F
PCI Express^®
GbE, 10 GbE
SRIO
SerDes lanes
Package
P5020/P5010
2x 64-bit e5500, 1x (P5010)
2/1 (single thread per core)
1.6 to 2.0 GHz
512 KB per core
2 MB (P5020)/1 MB (P5010)
2x 64-bit DDR3 (up to 1333 MT/s)
1x 64-bit DDR3 (P5010)
4x PCIe v2.0
5x 1 GbE, 1x 10 GbE
2x SRIO v2.1
(supports Type 9 and 11 messaging)
18 lanes
1295-pin 37.5 x 37.5 mm FC-PBGA
P5040/P5021
4x 64-bit e5500, 2x (P5021)
4/2 (single thread per core)
1.8 to 2.4 GHz
512 KB per core
2 MB (both P5040 and P5021)
2x 64-bit DDR3 (up to 1600 MT/s)
3x PCIe v2.0 (incl. 1 x 8)
10x 1 GbE, 2x 10 GbE
N/A
20 lanes
1295-pin 37.5 x 37.5 mm FC-PBGA
e5500 Core
The P5020 is based on the 64-bit e5500 Power
Architecture^® core. The e5500 core uses a
seven-stage pipeline for low latency response to
unpredictable code execution paths, boosting its
single-threaded performance. Key features:
• Supports up to 2.0 GHz core frequencies
• Tightly-coupled low latency cache hierarchy:
32 KB I/D (L1), 512 KB L2 per core
• Up to 2 MB of shared platform cache (L3)
• 3.0 DMIPS/MHz per core
• Up to 64 GB of addressable memory space
• Hybrid 32-bit mode to support legacy software
and seamless transition to 64-bit architecture
Virtualization
The P5020 includes support for hardware-
assisted virtualization. The e5500 core offers
an extra core privilege level (hypervisor).
Virtualization software for the P5 family includes
kernel-based virtual machine (KVM), Linux^®
containers, Freescale hypervisor and commercial
virtualization software from Green Hills^® Software
and Enea^®.