P1021NXE2FFB Datasheet, PDF (1/2 Pages) Freescale Semiconductor, Inc – communications processors

QorIQ Communications Platforms
P Series
QorIQ P1012 and P1021
communications processors
Overview
Freescale QorIQ communications platforms are
the next-generation evolution of our leading
PowerQUICC communications processors. Built
using high-performance Power Architecture^®
cores, QorIQ platforms enable a new era of
networking innovation where the reliability,
security and quality of service for every
connection matters.
QorIQ P1012 and P1021
Communications Processors
The QorIQ P1 family, which includes the P1012
and P1021 communications processors, offers
the value of smart integration and efficient power
intelligence for a wide variety of applications in
the networking, telecom, defense and industrial
markets. Based on 45 nm technology for low
power, the P1012 and P1021 processors provide
single- and dual-core options, from 533 MHz–
800 MHz, along with advanced security and a
rich set of interfaces.
The P1012 and P1021 processors are ideally
suited for multiservice gateways, Ethernet switch
controllers, wireless LAN access points and high-
performance general-purpose control processor
applications with tight thermal constraints.
The P1012 and P1021 processors are pin-
compatible with the QorIQ P1011, P1020 and
P2 platform products, offering a six-chip range
of cost-effective solutions. Scaling from a single
core at 533 MHz (P1012) to a dual core at 1.2
GHz per core (P2020), the combined QorIQ
platforms deliver an impressive 4.5x aggregate
frequency range.
The P1012 and P1021 platforms are fully
software compatible, both featuring the e500
Power Architecture core and peripherals, as
well as being fully software compatible with the
earlier PowerQUICC processors. This enables
customers to create a product with multiple
performance points from a single board design.
The QorIQ P1021 dual-core processor supports
both symmetric and asymmetric processing,
enabling customers to further optimize their
design with the same applications running on
each core or serialize your application using the
cores for different processing tasks.
The P1012 and P1021 processors have an
advanced set of features for ease of use. The
256 KB L2 cache offers incremental configuration
to partition the cache between the two cores or
to configure it as SRAM or stashing memory.
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Security
Acceleration
XOR
Power Architecture^®
e500 Core
32 KB
32 KB
L1 I Cache L1 D Cache
256 KB
L2 Cache
Not on P1012
Power Architecture
e500 Core
32 KB
32 KB
L1 I Cache L1 D Cache
Coherency Module
System Bus
DDR2/DDR3
SDRAM Controller
DUART, 2x I²C, Timers,
Interrupt Control,
SD/MMC, SPI,
2x USB 2.0/ULPI
Enhanced Local Bus
Controller (eLBC)
QUICC Engine
3x
Gigabit
Ethernet
On-Chip Network
2x PCI
Express^®
4-ch. DMA
Controller
UTOPIA-L2 TDM Ethernet
4-lane SerDes
Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)
Accelerators and Memory Control
Networking Elements
Basic Peripherals and Interconnect