MSC7110 Datasheet, PDF (1/8 Pages) Freescale Semiconductor, Inc – Low-Cost 16-Bit DSP with DDR Controller

Freescale Semiconductor
Product Brief
MSC7110PB
Rev. 2, 12/2005
MSC7110
Low-Cost 16-Bit DSP with DDR Controller
JTAG Port
JTAG
DMA
(32 ch)
AMDMA
64
to IPBus
SC1400
Core
DSP
Extended
Core
Trace
Buffer
(8 KB)
Fetch
Unit
Instruction
Cache
(16 KB)
128
Extended
Core
Interface
64
AMIC
AMEC
128
64 64
P XA XB
M1
SRAM
(64 KB)
ASM1
64
Note: The arrows show the direction of the transfer.
ASM2
128
Boot ROM
(8 KB)
ASEMI
64
from
IPBus
ASTH
64
ASAPB
32
32
APB
External
Memory
Interface
External Bus
32
Host
Interface
(HDI16)
TDM
UART
GPIO
HDI16
Port
TDM
RS-232
GPIO
The MSC7110 device
targets high-bandwidth
highly computational
DSP applications and
is optimized for
Enterprise class packet
telephony applications,
providing a competitive
price per channel for
voice over packet
systems.
Watchdog
ASAPB
32
ASSB
32
32
to EMI
to DMA
to Crossbar
IPBus
Interrupt
Control
Interrupts
PLL/Clock
PLL/Clock
System Control
to/from OCE
Event Port
Events
Timers
I²C
I²C
Figure 1. MSC7110 Block Diagram
The MSC7110 device is a highly integrated DSP processor that contains the StarCore™ SC1400 core, 64 KB of
SRAM memory, a 16 KB ICache, an 8 KB boot ROM, a 128-channel time-division multiplexing (TDM) interface
with hardware support for µ/A-law decoding/encoding, a UART, a 32-channel DMA controller, a 16-bit host
interface (HDI16) to support an external host processor, a programmable interrupt controller (PIC), an I²C
interface, two 16-bit quad cascadable timers, GPIO signals, and an on-chip emulator (OCE) and event port for
enhanced debug capability. The SC1400 core has four ALUs and performs at 1000 DSP million multiply
accumulates per second (MMACS) with an internal 266 MHz clock at 1.2 V.
© Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.