MPC92433 Datasheet, PDF (1/20 Pages) Freescale Semiconductor, Inc – 1428 MHz Dual Output LVPECL Clock Synthesizer

Freescale Semiconductor
Technical Data
1428 MHz Dual Output LVPECL
Clock Synthesizer
The MPC92433 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance
telecom, networking, and computing applications. With output frequencies from
42.50 MHz to 1428 MHz and the support of two differential PECL output signals,
the device meets the needs of the most demanding clock applications.
Features
• 42.50 MHz to 1428 MHz synthesized clock output signal
• Two differential, LVPECL-compatible high-frequency outputs
• Output frequency programmable through 2-wire I2C bus or parallel interface
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference clock input
• Synchronous clock stop functionality for both outputs
• LOCK indicator output (LVCMOS)
• LVCMOS compatible control inputs
• Fully integrated PLL
• 3.3 V power supply
• 48-lead LQFP
• 48-lead Pb-free package available
• SiGe Technology
• Ambient temperature range: –40°C to +85°C
Typical Applications
• Programmable clock source for server, computing, and telecommunication systems
• Frequency margining
• Oscillator replacement
MPC92433
Rev 2, 06/2005
MPC92433
1428 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
FA SUFFIX⁽¹⁾
48-LEAD LQFP PACKAGE
CASE 932-03
AE SUFFIX⁽²⁾
48-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 932-03
The MPC92433 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-
frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can
be changed on the fly for frequency margining purposes.
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS
compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a
selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2856 MHz. Its output
is scaled by a divider that is configured by either the I²C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL
pre-divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL
is internal.
The PLL post-divider N is configured through either the I²C or the parallel interfaces, and can provide one of seven division
ratios (2, 4, 6, 8, 12, 16, 32). This divider extends the performance of the part while providing a 50 Ω duty cycle. The high-
frequency outputs, Q_A and Q_B, are differential and are capable of driving a pair of transmission lines terminated 50 Ω to
V_CC – 2.0 V. The second high-frequency output, Q_B, can be configured to run at either 1x or 1/2x of the clock frequency or the
first output (Q_A). The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output
drivers to minimize noise induced jitter.
The configuration logic has two sections: I²C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB,
and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I²C
interface. The serial interface is I²C compatible and provides read and write access to the internal PLL configuration registers.
The lock state of the PLL is indicated by the LVCMOS-compatible LOCK output.
1. FA suffix: leaded terminations.
2. AE suffix: lead-free, EPP and RoHS-compliant.
© Freescale Semiconductor, Inc., 2005. All rights reserved.