MHVIC2115NR2 Datasheet, PDF (1/12 Pages) Freescale Semiconductor, Inc – RF LDMOS Wideband Integrated Power Amplifier

Freescale Semiconductor
Technical Data
Document Number: MHVIC2115NR2
Rev. 5, 5/2006
RF LDMOS Wideband Integrated
Power Amplifier
The MHVIC2115NR2 wideband integrated circuit is designed for base station
applications. It uses Freescale’s newest High Voltage (26 to 28 Volts) LDMOS
IC technology and integrates a multi - stage structure. Its wideband On - Chip
matching design makes it usable from 1600 to 2600 MHz. The linearity
performances cover W - CDMA modulation formats.
Final Application
• Typical W - CDMA Performance: - 45 dBc ACPR, 2110 - 2170 MHz, V_DD =
27 Volts, I_DQ1 = 56 mA, I_DQ2 = 61 mA, I_DQ3 = 117 mA, P_out = 34 dBm,
3GPP Test Model 1, Measured in 1.0 MHz BW @ 4 MHz offset, 64 DTCH
Power Gain — 30 dB
PAE = 16%
Driver Application
• Typical W - CDMA Performance: - 53 dBc ACPR, 2110 - 2170 MHz, V_DD =
26 Volts, I_DQ1 = 96 mA, I_DQ2 = 204 mA, I_DQ3 = 111 mA, P_out = 23 dBm,
3GPP Test Model 1, Measured in 3.84 MHz BW @ 5 MHz offset, 64 DTCH
Power Gain — 34 dB
• Gain Flatness = 0.3 dB from 2110 - 2170 MHz
• P1dB = 15 Watts, Gain Flatness = 0.2 dB from 2110 - 2170 MHz
• Capable of Handling 3:1 VSWR, @ 26 Vdc, 2140 MHz, 15 Watts CW
Output Power
Features
• Characterized with Series Equivalent Large - Signal Impedance Parameters
• On - Chip Matching (50 Ohm Input, DC Blocked, >5 Ohm Output)
• Integrated Temperature Compensation with Enable/Disable Function
• Integrated ESD Protection
• RoHS Compliant
• In Tape and Reel. R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.
Table 1. Maximum Ratings
MHVIC2115NR2
2170 MHz, 26 V, 23/34 dBm
W - CDMA
RF LDMOS WIDEBAND
INTEGRATED POWER AMPLIFIER
16
1
CASE 978 - 03
PFP - 16
Rating
Symbol
Value
Unit
Drain- Source Voltage
Gate- Source Voltage
Storage Temperature Range
Operating Junction Temperature
V_DSS
- 0.5, +65
Vdc
V_GS
- 0.5, +15
Vdc
T_stg
- 65 to +150
°C
T_J
150
°C
V_GS3
V_GS2
V_GS1
RF_in I_C
V_DS1
V_DS2
Quiescent Current
Temperature Compensation
3 Stages I_C
Figure 1. Block Diagram
V_DS3/RF_out
N.C. 1
V_GS3 2
V_GS2 3
V_GS1 4
RF_in 5
RF_in 6
V_DS1 7
V_DS2 8
16 N.C.
15 ^VDS3^/RFout
14 ^VDS3^/RFout
13 ^VDS3^/RFout
12 ^VDS3^/RFout
11 ^VDS3^/RFout
10 V_DS3/RF_out
9 ^N.C.
(Top View)
Note: Exposed backside flag is source
terminal for transistors.
Figure 2. Pin Connections
© Freescale Semiconductor, Inc., 2006. All rights reserved.
RF Device Data
Freescale Semiconductor
MHVIC2115NR2
1