MCF5485 Datasheet, PDF (1/30 Pages) Freescale Semiconductor, Inc – Integrated Microprocessor Electrical Characteristics

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF5485EC
Rev. 3, 03/2007
MCF5485
TEPBGA–388
MCF5485 Integrated
Microprocessor Electrical
Characteristics
This chapter contains electrical specification tables and
reference timing diagrams for the MCF5485 microprocessor.
This section contains detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications of the MCF5485.
MCF548X Family Features:
• ColdFire V4e Core
– Limited superscalar V4 ColdFire processor core
– Up to 200MHz peak internal core frequency (308 MIPS
(Dhrystone 2.1) @ 200 MHz)
– Harvard architecture
– 32-Kbyte instruction cache
– 32-Kbyte data cache
– Memory Management Unit (MMU)
– Floating point unit (FPU)
• Internal master bus (XLB) arbiter
• 32-bit double data rate (DDR) synchronous DRAM
(SDRAM) controller
– 66–133 MHz operation
• Version 2.2 peripheral component interconnect (PCI) bus
• Flexible multi-function external bus (FlexBus)
• Communications I/O subsystem
– Intelligent 16 channel DMA controller, with support for
– Dedicated DMA channels for receive and transmit on
all subsystem peripheral interfaces
– Up to two (2) 10/100 Mbps fast Ethernet controllers
(FECs)
– Universal serial bus (USB) version 2.0 device controller
– Up to four (4) programmable serial controllers (PSCs)
for UART, USART, modem, codec, and IrDA 1.1
interfaces
– I²C peripheral interface
– Two (2) controller area network 2.0B controllers
– DMA Serial Peripheral Interface (DSPI)
• Optional Cryptography accelerator module
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random Number Generator
• 32-Kbyte system SRAM
• System integration unit (SIU)
– Interrupt controller
– Watchdog timer
– Two (2) 32-bit slice timers
– Up to four (4) 32-bit general-purpose timers
– General-purpose I/O ports multiplexed with peripheral
pins
• Debug and test features
– ColdFire background debug mode (BDM) port
– JTAG/ IEEE 1149.1 test access port
• PLL and clock generator
– 30 to 66.67 MHz input frequency range
© Freescale Semiconductor, Inc., 2007. All rights reserved.