MCF51CN128 Datasheet, PDF (1/48 Pages) Freescale Semiconductor, Inc – MCF51CN128 ColdFire Microcontroller

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51CN128
Rev. 4, 5/2009
MCF51CN128 ColdFire
Microcontroller
Cover: MCF51CN128
MCF51CN128
80 LQFP
14 mm × 14 mm
64 LQFP
10 mm × 10 mm
48 QFN
7 mm × 7 mm
The MCF51CN128 device is a low-cost, low-power,
high-performance 32-bit ColdFire V1 microcontroller (MCU)
featuring 10/100 BASE-T/TX fast ethernet controller (FEC),
media independent interface (MII) to connect an external
physical transceiver (PHY), and multi-function external bus
interface.
MCF51CN128 also has multiple communication interfaces
for various ethernet gateway applications. MCF51CN128 is
the first ColdFire V1 device to incorporate ethernet and
external bus interface along with new features to minimize
power consumption and increase functionality in low-power
modes.
The MCF51CN128 features the following functional units:
• 32-bit ColdFire V1 Central Processing Unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up
to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz
CPU from 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash)
– ColdFire Instruction Set Revision C (ISA_C)
– Support for up to 45 peripheral interrupt requests and 7
software interrupts
• On-Chip Memory
– 128 KB Flash, 24 KB RAM
– Flash read/program/erase over full operating voltage
and temperature
– On-chip memory aliased to create a contiguous memory
space with off-chip memory
– Security circuitry to prevent unauthorized access to
Peripherals, RAM, and flash contents
• Ethernet
– FEC—10/100 BASE-T/TX, bus-mastering fast ethernet
controller with direct memory access (DMA); supports
half or full duplex; operation is limited to 3.0 V to 3.6 V
– MII—media independent interface to connect ethernet
controller to external PHY; includes output clock for
external PHY
• External Bus
– Mini-FlexBus—Multi-function external bus interface;
supports up to 1 MB memories, gate-array logic, simple
slave device or glueless interfaces to standard
chip-selected asynchronous memories
– Programmable options: access time per chip select, burst
and burst-inhibited transfers per chip select, transfer
direction, and address setup and hold times
• Power-Saving Modes
– Two low-power stop modes, one of which allows limited
use of some peripherals (ADC, KBI, RTC)
– Reduced-power wait mode shuts off CPU and allows
full use of all peripherals; FEC can remain active and
conduct DMA transfers to RAM and assert an interrupt
to wake up the CPU upon completion
– Low-power run and wait modes allow peripherals to run
while the voltage regulator is in standby
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low-power external oscillator that can be used in stop3
mode to provide accurate clock source to active
peripherals
– Low-power real-time counter for use in run, wait, and
stop modes with internal and external clock sources
– 6 μs typical wake-up time from stop3 mode
– Pins and clocks to peripherals not available in smaller
packages are automatically disabled for reduced current
consumption; no user interaction is needed
• Clock Source Options
– Oscillator (XOSC) — Loop-control pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 25 MHz
– Multi-Purpose Clock Generator (MCG) — Flexible
clock source module with either frequency-locked-loop
(FLL) or phase-lock loop (PLL) clock options. FLL can
be controlled by internal or external reference and
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.