MC100ES6221 Datasheet, PDF (1/12 Pages) Freescale Semiconductor, Inc – Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer

Freescale Semiconductor
Technical Data
MC100ES6221
Rev 5, 04/2005
Low Voltage 1:20 Differential
ECL/PECL/HSTL Clock Fanout Buffer
MC100ES6221
The MC100ES6221 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6221
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver is high performance clock
distribution in computing, networking and telecommunication systems.
LOW VOLTAGE DUAL
1:20 DIFFERENTIAL ECL/PECL/HSTL
CLOCK FANOUT BUFFER
Features
• 1:20 differential clock fanout buffer
• 100 ps maximum device skew
• SiGe technology
• Supports DC to 2 GHz operation of clock or data signals
• ECL/PECL compatible differential clock outputs
• ECL/PECL/HSTL compatible differential clock inputs
• Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
• Standard 52 lead LQFP package with exposed pad for enhanced thermal
characteristics
• Supports industrial temperature range
• Pin and function compatible to the MC100EP221
• 52-lead Pb-free Package Available
Functional Description
TB SUFFIX
52-LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A-01
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 1336A-01
The MC100ES6221 is designed for low skew clock distribution systems and
supports clock frequencies up to 2 GHz. The device accepts two clock sources.
The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The
selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If V_BB is connected to the CLK0 or CLK1 input
and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the
V_BB bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6221 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6221 supports positive (PECL) and negative (ECL) supplies. The MC100ES6221 is pin and function compatible to the
MC100EP221.
© Freescale Semiconductor, Inc., 2005. All rights reserved.