MC100ES60T22 Datasheet, PDF (1/8 Pages) Freescale Semiconductor, Inc – 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator

Freescale Semiconductor
Technical Data
3.3 V Dual LVTTL/LVCMOS to
Differential LVPECL Translator
The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential
LVPECL translator. The low voltage PECL levels, small package, and dual gate
design are ideal for clock translation applications.
Features
• 280 ps typical propagation delay
• 100 ps max output-to-output skew
• LVPECL operating range: V_CC = 3.135 V to 3.8 V
• 8-lead SOIC and 8-lead TSSOP packages
• Ambient temperature range –40°C to +85°C
MC100ES60T22
Rev 2, 2/2005
MC100ES60T22
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
Q0 1
Q0 2
LVPECL
Q1 3
8 V_CC
7 D0
LVTTL/LVCMOS
6 D1
Q1 4
5 GND
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 1640-01
ORDERING INFORMATION
Device
Package
MC100ES60T22D
SOIC-8
MC100ES60T22DR2
SOIC-8
MC100ES60T22DT
TSSOP-8
MC100ES60T22DTR2
TSSOP-8
Pin
D0, D1
Qn, Qn
V_CC
GND
PIN DESCRIPTION
Function
LVTTL/LVCMOS Inputs
LVPECL Differential Outputs
Positive Supply
Negative Supply
© Freescale Semiconductor, Inc., 2005. All rights reserved.