K40P104M100SF2 Datasheet, PDF (1/60 Pages) Freescale Semiconductor, Inc – K40 Sub-Family Data Sheet

Freescale Semiconductor
Data Sheet: Product Preview
Document Number: K40P104M100SF2
Rev. 1, 11/2010
K40P104M100SF2
K40 Sub-Family Data Sheet
Supports the following:
MK40N512VLL100, MK40N512V.L100
Features
• ^{Human-machine interface}
• ^{Operating Characteristics}
– Segment LCD controller supporting up to 40
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• ^Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• ^{Memories and memory interfaces}
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 128 KB RAM
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
y _{• Analog modules}
r – 16-bit SAR ADC with PGA (x64)
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
a _{and programmable reference input}
– Voltage reference
in ^{• Timers}
– Serial programming interface (EzPort)
• ^Clocks
– 1 to 32 MHz crystal oscillator
lim ^{– 32 kHz crystal oscillator}
– Multi-purpose clock generator
• ^{System peripherals}
– 10 low-power modes to provide power optimization
based on application requirements
e _{– Memory protection unit with multi-master}
r ^protection
– 16-channel DMA controller, supporting up to 64
request sources
P ^{– External watchdog monitor}
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timers
– Two-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
• ^{Communication interfaces}
– USB full-/low-speed On-the-Go controller with on-
chip transceiver
– Controller Area Network (CAN) module
– SPI modules
– Software watchdog
– I2C modules
– Low-leakage wakeup unit
– UART modules
• ^{Security and integrity modules}
– Hardware CRC module to support fast cyclic
– Secure Digital host controller (SDHC)
– I2S
redundancy checks
– Hardware random-number generator
– 128-bit unique identification (ID) number per chip
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2010 Freescale Semiconductor, Inc.
Preliminary