DSP56303_1 Datasheet, PDF (1/108 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

Freescale Semiconductor
Technical Data
DSP56303
Rev. 11, 2/2005
DSP56303
24-Bit Digital Signal Processor
16
66
3
Triple
Timer
HI08
ESSI
SCI
Address
Generation
Unit
Six-Channel
DMA Unit
Bootstrap
ROM
Peripheral
Expansion Area
EXTAL
XTAL
Internal
Data
Bus
Switch
Clock
Generator
PLL
Program
Interrupt
Controller
Program
Decode
Controller
2
RESET
PINIT/NMI
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Memory Expansion Area
PrograM
RAM
4096 × 24
bits
(default)
X Data
RAM
2048 × 24
bits
(default)
Y Data
RAM
2048 × 24
bits
(default)
YAB
XAB
PAB
DAB
External
18
Address
Bus
Switch
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
External
Bus
13
Interface
and Inst.
Cache ^Control
Control
External
Data Bus
Switch
24
Data
Program
Address
Generator
Power
Management
Data ALU
5
24 × 24 ⁺ 56 ^→56-bit MAC
JTAG
Two 56-bit Accumulators
56-bit Barrel Shifter
OnCE™
DE
Figure 1. DSP56303 Block Diagram
The DSP56303 is intended
for use in telecommunication
applications, such as multi-
line voice/data/ fax
processing, video
conferencing, audio
applications, control, and
general digital signal
processing.
What’s New?
Rev. 11 includes the following
changes:
• Adds lead-free packaging and
part numbers.
The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural
features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The
DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family
offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable
wireless, telecommunications, and multimedia products.
© Freescale Semiconductor, Inc., 1996, 2005. All rights reserved.