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AN2407 Datasheet, PDF (1/48 Pages) Freescale Semiconductor, Inc – Reed Solomon Encoder/Decoder on the StarCore SC140/SC1400 Cores, With Extended Examples
Freescale Semiconductor
Application Note
AN2407
Rev. 1, 12/2004
Reed Solomon Encoder/Decoder on
the StarCore™ SC140/SC1400 Cores,
With Extended Examples
By Jasmin Oz and Assaf Naor
This application note describes the implementation of the Reed-
Solomon error-control codes on the StarCore™ SC140 DSP
core. Reed-Solomon codes are the preferred error-control
coding procedures in a wide range of applications, such as
ADSL, digital cellular phones, storage devices, and deep-space
communications. Their popularity originates from their strong
capability to correct both random and burst errors.
The current trend for improving DSP-processing speed is to
place multiple processor units on a single chip with an
architecture that supports parallel execution. The StarCore
SC140 family of DSPs exemplifies this trend. It has four data-
arithmetic units (DALUs) and two address-generation units
(AGUs). Code implementation for these processors should
capitalize on their capabilities. This document describes the
implementation of the Reed-Solomon encoder and decoder on
the SC140 core. The document begins with a basic theoretical
background on the Reed-Solomon algorithm and then discusses
the implementation of the encoder and decoder. Little or no
background on the subject is required.
CONTENTS
1 Basics of Forward Error Correction (FEC) .............2
2 Theory ..................................................................... 3
2.1 Galois Fields ........................................................... 3
2.2 Reed-Solomon Codes ..............................................6
2.3 Error-Correcting Performance of
Reed-Solomon Codes ..............................................9
3 SC140 Core Overview ..........................................10
4 Implementation on the SC140 Core.......................12
4.1 Polynomial Evaluation Over GF(256) .................. 13
4.2 MAC Instructions Over Galois Fields ..................14
4.3 Look-up Tables .....................................................14
4.4 Lowest Cycle Count Limit for Polynomial
Evaluation .............................................................15
4.5 Cycle Count of the Reed-Solomon Routines ........16
5 Results................................................................... 17
6 Summary ............................................................... 19
7 References .............................................................19
© Freescale Semiconductor, Inc., 2003, 2004. All rights reserved.