AK4116-B Datasheet, PDF (4/19 Pages) Asahi Kasei Microsystems – Evaluation Board

ASAHI KASEI
[AKD4116-B]
c. ΦʔσΟΦϑΥʔϚοτ
DIF2-0 bitΛઃఆͯ͠Լ͍͞
Mode
0
1
2
3
4
5
6
7
DIF2
bit
0
0
0
0
1
1
1
1
DIF1
bit
0
0
1
1
0
0
1
1
DIF0
bit
0
1
0
1
0
1
0
1
DAUX
SDTO
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I²S
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I²S
Reserved
Table 3. Audio format
LRCK
I/O
H/L O
H/L O
H/L O
H/L O
H/L O
L/H O
Default
d. CM1, CM0ͷઃఆ
PLLͷಈ࡞ϞʔυͷઃఆΛߦ͍·͢ɻCM1-0 bitʹͯઃఆΛߦ͍·͢ɻ
CM1 bit CM0 bit (UNLOCK) PLL
SDTO
X'tal
Clock source
source
0
0
-
ON ON(Note 1) PLL(RX)
RX
0
1
1
0
-
OFF
ON
X'tal
DAUX
0
ON
ON
PLL(RX)
RX
1
ON
ON
X'tal
DAUX
1
1
-
ON
ON
X'tal
DAUX
ON:ൃৼ (Power-up), OFF:ൃৼఀࢭ (Power-Down)
Note 1: X’talΛϦϑΝϨϯεΫϩοΫʹ࢖༻͠ͳ͍৔߹(XTL0,1= “1,1”)͸OFFͰ͢ɻ
Table 4. Clock Operation Mode Select
Default
<KM077400>
-4-
2005/01