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AKD4103A-B Datasheet, PDF (3/26 Pages) Asahi Kasei Microsystems – DIT | |||
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[AKD4103A-B]
CKS1 pin
(SW3_5)
CKS1 bit
CKS0 pin
(Sub_JP19)
CKS0 bit
MCLK
fs (max)
0
0
128fs
28k-192 kHz
0
1
256fs
28k-108 kHz
1
0
384fs
28k-54 kHz
1
1
512fs
28k-54 kHz
Table 3. Master Clock Frequency Select
Default
b-1. BICK, LRCKã®å
¥åºåã«è¨å®
AK4103Aã®ãªã¼ãã£ãªãã©ã¼ãããã®è¨å®(Table 5åç
§)ã«å¾ã£ã¦SW3_8(DIT_I/O)ã®è¨å®ãè¡ã£ã¦
ä¸ããã
åºåä¿¡å·
SW3_8 (DIT_I/O)
ã¹ã¬ã¼ãã¢ã¼ãæ
0
ãã¹ã¿ã¼ã¢ã¼ãæ
1
Table 4. DIT_I/Oã®è¨å®
Default
c. ãªã¼ãã£ãªãã©ã¼ããã
åæã¢ã¼ãæã¯SW1_2, SW1_3, SW1_4ã§è¨å®ãã¾ããéåæã¢ã¼ãæã¯DIF2-0 bitãè¨å®ãã¦ä¸ãã
Mode
0
1
2
3
4
5
6
7
DIF2 pin
(SW1_4)
DIF2 bit
0
0
0
0
1
1
1
1
DIF1 pin
(SW1_3)
DIF1 bit
0
0
1
1
0
0
1
1
DIF0 pin
(SW1_2)
SDTI
DIF0 bit
0
16bit, Right justified
1
18bit, Right justified
0
20bit, Right justified
1
24bit, Right justified
0
24bit, Left justified
1
24bit, I2S
0
24bit, Left justified
1
24bit, I2S
Table 5. Audio format
LRCK
I/O
H/L I
H/L I
H/L I
H/L I
H/L I
L/H I
H/L O
L/H O
BICK
I/O
32fs-128fs I
36fs-128fs I
40fs-128fs I
48fs-128fs I
48fs-128fs I
50fs-128fs I
64fs
O
64fs
O
Default
<KM076803>
-3-
2011/07
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