FXO-PC735RGB-312 Datasheet, PDF (2/3 Pages) Fox Electronics – LVPECL 7 x 5mm 3.3V 50ppm XO Freq: 312.5MHz

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Model: FXO-PC735RGB-312
LVPECL 7 x 5mm 3.3V 50ppm XO Freq: 312.5MHz
Dimensional Drawing & Pad Layout
Phase Jitter & Time Interval Error (TIE) (Typical Measurements)
Frequency
Phase Jitter
(12kHz to 20MHz)
TIE
(Sigma of Jitter Distribution)
Units
312.5 MHz
0.86
3.5
pS RMS
Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; V_DD = 3.3V.
TIE was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; V_DD = 3.3V.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Random & Deterministic Jitter Composition (Typical Measurements)
Random (Rj) Deterministic (Dj)
Frequency
(pS RMS)
(pS P-P)
Total Jitter (Tj)
(14 x Rj) + Dj
312.5 MHz
1.29
9.3
27.7 pS
Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Pin Functional Description
Pin #
1
2
3
4
Name
E/D¹
2
NC
GND
Output
Type
Logic
Ground
Output
Function
Enable / Disable Control of Output (0 = Disabled)
No Connection – Leave Open
Electrical Ground for V_DD
LVPECL Oscillator Output
5
6
NOTES:
Output 2
Output
Complementary LVPECL Output
V_DD ³
Power
Power Supply Source Voltage
1
Includes pull-up resistor to V_DD to provide output when the pin (1) is No Connect. (Also see note 2)
2
An optional pin # 2 Enable / disable is available.
3
Installation should include a 0.01µF bypass capacitor placed between V_DD
(Pin 6) and GND (Pin 3) to minimize power supply line noise.
DWG-100725 | Rev. 6/2/2010
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