F71889A Datasheet, PDF (37/132 Pages) Feature Integration Technology Inc. – Super Hardware Monitor + LPC I/O

3
TSI 02_SEL
2
TSI 01_SEL
1-0
Reserved
F71889A
If this bit is set to 1, CR7B is able to be written and can also be used
R/W 0
to control fan.
If this bit is set to 1, CR7A is able to be written and can also be used
R/W 0
to control fan.
-
0 ^Reserved.
TSI Offset Register ⎯ Index 08h
Bit
Name
R/W Default
Description
When PECI and AMD TSI/Intel IBX are enabled at the same time,
this byte is used as the offset to be added to the CPU temperature
reading of AMD_TSI/Intel IBX. To using this byte as offset of AMD
7-0 TSI_OFFSET R/W 0
TSI/Intel IBX CPU temperature reading, the TSI_OFFSET_SEL in
CR08 must be set to 1.
The range of this register is -128 ~ 127.
SST and VTT_SEL Register ⎯ Index 0Ah
Bit
Name
R/W Default
Description
7-5
Reserved
-
0 ^Reserved.
Set this bit “1” and select Intel model will enable SST interface.
4
SST_EN_REG R/W
0 Otherwise will disable SST interface
This bit is cleared by LRESET#.
PECI (Vtt) voltage select.
00: Vtt is 1.23V
3-2
VTT_SEL
R/W 0 01: Vtt is 1.13V
10: Vtt is 1.00V
11: Vtt is 1.00V
1
DIG_T1_EN
R/W
0
0: Disable the digital interface of T1 (PECI/TSI).
1: Enable the digital interface of T1.
0
DIODE_T1_EN R/W
1
0: Disable the D1+ measurement.
1: Enable the D1+ measurement.
PECI Address Register ⎯ Index 0Bh
Bit
Name
R/W Default
Description
Select the Intel CPU socket number.
0000: no CPU presented. PECI host will use Ping() command to find CPU
address.
7-4
CPU_SEL
R/W
0
0001: CPU is in socket 0, i.e. PECI address is 0x30.
0010: CPU is in socket 1, i.e. PECI address is 0x31.
0100: CPU is in socket 2, i.e. PECI address is 0x32.
1000: CPU is in socket 3, i.e. PECI address is 0x33.
Otherwise are reserved.
3-1
Reserved
-
0 ^Reserved.
0
DOMAIN1_EN
R/W
0
If the CPU selected is dual core. Set this register 1 to read the temperature
of domain1.
-33-
Sep, 2011
V0.21P