F75125 Datasheet, PDF (21/34 Pages) Feature Integration Technology Inc. – Serial VID, Parallel VID Translator for AMD AM2 and AM2+

Fintek
Feature Integration Technology Inc.
Note:
*1 SVID_IN[7] is output by the processor to the F75125
*2 SVID_OUT[7] is output by the F75125 to the Vcore voltage regulator
F75125
6.6 CORE_TYPE
The CORE_TYPE is used to indicate which kind of processor placed and which kind of VID codes should be issued
by the processor. According to AMD’s reference circuit, the VID[1] is recommended tied with CORE_TYPE. In AM2,
CORE_TYPE is floating, and VID[1] is driven to VDDIO by the processor. The processor will issue the parallel VID
codes. In AM2+, CORE_TYPE is tied to VSS at the package, and VID[1] is driven low via strap to ground. The
processor will issue the serial VID codes. CORE_TYPE is also connected to the F75125 to indicate which kind of
VID codes will be decoded.
6.7 Voltage Sense Input/ Voltage Sense Output
The Voltage Sense Input (VSI) and Voltage Sense Output (VSO) are designed for another option of over voltage,
especially beyond the VID table, 1.55V. Every step of over voltage is 1.5% more of the current voltage. Total tuning
steps are 32 steps, so the maximum tuning range up is to 2.325V.
VREF
F72815
+
_
Multi-phase PWM
VI
Vout
+
Vout
_ ^VREF
VSO
VSI
VSO
VSI
F75125
F75125
Vout=VREF*(1+n*0.01613) n=0,1,2……31
Figure 4 VSI/VSO function illustration
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V0.16P