FWLF1631 Datasheet, PDF (3/10 Pages) Finisar Corporation. – DWDM SFP Transceiver

FWLF-1631-xx DWDM SFP – June 2009
Finisar
I. Pin Descriptions
Pin
Symbol
Name/Description
Ref.
1
V_EET
Transmitter Ground (Common with Receiver Ground)
1
2
T_FAULT
Transmitter Fault
3
T_DIS
Transmitter Disable. Laser output disabled on high or open
2
4 MOD_DEF(2) Module Definition 2. Data line for Serial ID
3
5 MOD_DEF(1) Module Definition 1. Clock line for Serial ID
3
6 MOD_DEF(0) Module Definition 0. Grounded within the module
3
7
Rate Select No connection required
4
8
LOS
Loss of Signal indication. Logic 0 indicates normal operation
5
9
V_EER
Receiver Ground (Common with Transmitter Ground)
1
10
V_EER
Receiver Ground (Common with Transmitter Ground)
1
11
V_EER
Receiver Ground (Common with Transmitter Ground)
1
12
RD-
Receiver Inverted DATA out. AC Coupled
13
RD+
Receiver Non-inverted DATA out. AC Coupled
14
V_EER
Receiver Ground (Common with Transmitter Ground)
1
15
V_CCR
Receiver Power Supply
16
V_CCT
Transmitter Power Supply
17
V_EET
Transmitter Ground (Common with Receiver Ground)
1
18
TD+
Transmitter Non-Inverted DATA in. 100 ohm termination between TD+
and TD-, AC Coupled thereafter
19
TD-
Transmitter Inverted DATA in. See TD+
20
V_EET
Transmitter Ground (Common with Receiver Ground)
1
Notes:
1. Circuit ground is internally isolated from chassis ground.
2. Laser output disabled on T_DIS >2.0V or open, enabled on T_DIS <0.8V.
3. Should be pulled up with 4.7k – 10kohms on host board to a voltage between 2.0V and 5.5V.
MOD_DEF(0) pulls line low to indicate module is plugged in.
4. Receiver achieves multi-rate operation without active control.
5. LOS is open collector output. Should be pulled up with 4.7k – 10kohms on host board to a voltage between 2.0V
and 5.5V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.
Towards
Bezel
VeeT
20
1
VeeT
TD-
19
2
TXFault
TD+
18
3
TX Disable
VeeT
17
4
MOD-DEF(2)
VccT
16
5
MOD-DEF(1)
VccR
15
Towards
6
MOD-DEF(0)
ASIC
VeeR
14
7
Rate Select
RD+
13
8
LOS
RD-
12
9
VeeR
VeeR
11
10
VeeR
Diagram of Host Board Connector Block Pin Numbers and Names
© Finisar Corporation
Page 3 June 2009 Rev E2