FTLX1461E2 Datasheet, PDF (2/10 Pages) Finisar Corporation. – RoHS-6 Compliant 10Gb/s 1310nm Single Mode XENPAK Transponder

FTLX1461E2 Product Specification – October 2008
I. PIN DESCRIPTION
Signal Name Level
I/O
Management and Monitoring Ports
MDIO
Open Drain
I/O
MDC
PRTAD4
PRTAD3
PRTAD2
PRTAD1
PRTAD0
LASI
1.2 V
I
CMOS
1.2 V
1
CMOS
1.2 V
I
CMOS
1.2 V
I
CMOS
1.2 V
I
CMOS
1.2 V
I
CMOS
Open Drain
O
RESET
Open Drain
I
Vendor Specific
TX ON/OFF Open Drain
I
MOD DETECT
O
Transmit Functions
Reserved
I
Reserved
I
TX LANE 3– AC-coupled,
I
TX LANE 3+ Internally biased I
TX LANE 2– ^differential
I
TX LANE 2+ ^XAUI
I
TX LANE 1–
I
TX LANE 1+
I
TX LANE 0–
I
TX LANE 0+
I
Pin No.
17
18
19
20
21
22
23
9
10
11,15,16,24
12
14
68
67
65
64
62
61
59
58
56
55
Description
Management Data I/O. Requires
external 10 - 22 kΩ pull-up to the
APS on host.
Management Data Clock Input
Port Address Input bit 4
Port Address Input bit 3
Port Address Input bit 2
Port Address Input bit 1
Port Address Input bit 0
Link Alarm Status Interrupt Output.
Open Drain Compatible Output with
10 - 20 kΩ pull-up on host.
Logic high = Normal Operation
Logic low = Status Flag Triggered
Reset Input.
Open Drain Compatible Input with
22 kΩ pull-up to APS internal to
transponder.
Logic high = Normal Operation
Logic low = RESET
Vendor Specific Pins.
Leave unconnected when not used.
TX ON/OFF Input.
Open Drain Compatible Input with
22 kΩ pull-up to APS internal to
transponder.
Logic high = Transmitter On
Logic low = Transmitter Off
Pulled low inside transponder
through a 1 kΩ resistor to Ground
Reserved For Future Use
Reserved For Future Use
Module XAUI Input Lane 3–
Module XAUI Input Lane 3+
Module XAUI Input Lane 2–
Module XAUI Input Lane 2+
Module XAUI Input Lane 1–
Module XAUI Input Lane 1+
Module XAUI Input Lane 0–
Module XAUI Input Lane 0+
© Finisar Corporation – October 2008
Rev B
Page 2