LPD200 Datasheet, PDF (1/2 Pages) Filtronic Compound Semiconductors – HIGH PERFORMANCE PHEMT

LPD200
HIGH PERFORMANCE PHEMT
• FEATURES
♦ 21 dBm Output Power at 1-dB
Compression at 18 GHz
♦ 12 dB Power Gain at 18 GHz
♦ 1.0 dB Noise Figure at 18 GHz
♦ 55% Power-Added Efficiency
GATE
BOND
PAD (2X)
DRAIN
BOND
PAD (2X)
SOURCE
BOND
PAD (2x)
• DESCRIPTION AND APPLICATIONS
DIE SIZE: 12.6X10.2mils (320x260 µm)
DIE THICKNESS: 3.9 mils (100 µm)
BONDING PADS: 3.3X2.6 mils (85x65 µm)
The LPD200 is an Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs)
Pseudomorphic High Electron Mobility Transistor (PHEMT), utilizing an Electron-Beam direct-
write 0.25 µm by 200 µm Schottky barrier gate. The recessed “mushroom” gate structure minimizes
parasitic gate-source and gate resistances. The epitaxial structure and processing have been
optimized for high dynamic range. The LPD200 also features Si₃N₄ passivation and is available in
various packages, such as ceramic P70 and other plastic packages.
Typical applications include use in low noise, broadband amplifiers.
• ELECTRICAL SPECIFICATIONS @ T_Ambient = 25°C
Parameter
Saturated Drain-Source Current
Power at 1-dB Compression
Power Gain at 1-dB Compression
Power-Added Efficiency
Maximum Drain-Source Current
Transconductance
Gate-Source Leakage Current
Pinch-Off Voltage
Gate-Source Breakdown
Voltage Magnitude
Gate-Drain Breakdown
Voltage Magnitude
Thermal Resistivity
frequency=18 GHz
Symbol
I_DSS
P-1dB
G-1dB
PAE
I_MAX
G_M
I_GSO
V_P
|V_BDGS|
|V_BDGD|
Θ_JC
Test Conditions
V_DS = 2 V; V_GS = 0 V
V_DS = 5 V; I_DS = 50% I_DSS
V_DS = 5 V; I_DS = 50% I_DSS
V_DS = 5 V; I_DS = 50% I_DSS
V_DS = 2 V; V_GS = 1 V
V_DS = 2 V; V_GS = 0 V
V_GS = -5 V
V_DS = 2 V; I_DS = 1 mA
I_GS = 1 mA
I_GD = 1 mA
Min Typ Max Units
40
60
85 mA
19
21
dBm
11 12.5
dB
55
%
125
mA
50
70
mS
1
10 µA
-0.25 -0.8 -1.5 V
-6
-7
V
-8
-9
V
260
°C/W
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Revised: 1/22/01
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