CMP0817BA8-I Datasheet, PDF (8/9 Pages) FIDELIX – 512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

CMP0817BA8-I
WRITE CYCLE (1) (/WE controlled)
Address
/CS
/UB, /LB
/WE
Data in
tAS(3)
High-Z
Data Out
Data Undefined
WRITE CYCLE (2) (/CS controlled, /WE=VIH)
Address
/CS
/UB, /LB
/WE
tAS(3)
Data in
Data Out
High-Z
CMOS LPRAM
tWC
tCW(2)
tAW
tBW
tWP(1)
tWHZ
tWR(4)
tDW
Data Valid
tDH
tOW
High-Z
tWC
tCW(2)
tAW
tBW
tWP(1)
tWR(4)
tDW
tDH
Data Valid
High-Z
WRITE CYCLE (3) (/UB, /LB controlled)
Address
/CS
/UB, /LB
/WE
tAS(3)
Data in
Data Out
High-Z
tWC
tCW(2)
tAW
tBW
tWP(1)
tWR(4)
tDW
tDH
Data Valid
High-Z
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us.
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Revision 0.3
Sep. 2006