CMP0417AAX-E Datasheet, PDF (7/12 Pages) FIDELIX – 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

CMP0417AAx-E
READ CYCLE (1) (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
CMOS LPRAM
Data Valid
READ CYCLE (2) (/ZZ=/WE=VIH)
Address
/CS
/UB, /LB
/OE
Data Out
High-Z
tRC
tAA
tCO
tBA
tOE
tOLZ
tBLZ
tLZ
Data Valid
tOH
tHZ
tBHZ
tOHZ
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 160us.
PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access)
A0~A3
A4~A20
tRC
tAA
tMRC
tPC
tPC
tPC
tPC
tPC
tPC
tPC
/CS
/UB, /LB
/OE
Data Out
High-Z
tOH
tCO
tHZ
tBA
tOE
tOLZ
tBLZ
tLZ
tBHZ
tPAA
tPAA
tPAA
tPAA
tPAA
tPAA
tPAA
tOHZ
Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 160us.
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Revision 0.5
Aug. 2006