FMP1617DA0 Datasheet, PDF (2/9 Pages) FIDELIX – 1M x 16bit Super Low Power and Low Voltage Full CMOS RAM

FMP1617DA0(7)
CMOS LPRAM
1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
FEATURES
• Process Technology : Full CMOS
• Organization : 1M x 16
• Power Supply Voltage : 2.7~3.3V
• Three state output and TTL Compatible
• Separated I/O power(VCCQ) & Core power(VCC)
• Operating Temperature Ranges:
Special (-10’C to +60’C)
Commercial (0’C to +70’C)
Extended (-25’C to +85’C)
Industrial (-40’C to +85’C)
•Package Type : 48-FBGA-6.00x8.00 mm²
FMP1617DA0(7)-HxxX : Pb-Free & Halogen Free
• Dual CS & Page Mode
FMP1617DA0 : Dual CS
FMP1617DA7 : Page mode with Dual CS
• Page read/write operation by 16 words
PRODUCT FAMILY
Product Family
Operating
Voltage (V)
Speed
Min. Typ. Max.
ICC1
f = 1MHz
Typ.
Max.
Power Dissipation
ICC2
f = fmax
Typ.
Max.
ISB1
(CMOS Standby
Current)
Typ.
Max.
FMP1617DA0(7)-H60E
FMP1617DA0(7)-H70E
2.7 3.0 3.3
60ns
70ns
1.5mA
3mA
15mA
12mA
20mA
70uA
100uA
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and T_A = 25C.
2. H=FBGA(Pb-Free & Halogen Free), W=WAFER
3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C)
PIN DESCRIPTION
1
23
4
5
6
FUNCTIONAL BLOCK DIAGRAM
A
/LB /OE A0
A1 A2 CS2
B
I/O9 /UB A3
A4 /CS I/O1
C
I/O10 I/O11 A5
A6 I/O2 I/O3
D
VSS I/O12 A17
A7 I/O4 VCC
Row
Addresses
Clk gen.
Row
select
Precharge circuit.
Memory array
VCC
VSS
E
VCCQ I/O13 DNU A16 I/O5 VSS
F
I/O15 I/O14 A14 A15 I/O6 I/O7
G
I/O16 A19 A12 A13 WE I/O8
H
A18
A8
A9
A10 A11
NC
48-FBGA : Top View(Ball Down)
Name
Function
Name
Function
CS2
Low Power Modes VCC
Core Power
/CS
Chip Select Input VCCQ
I/O Power
/OE
Output Enable Input VSS
Ground
/WE
Write Enable Input /UB Upper Byte(I/O9~16)
A0~A19
Address Inputs
/LB Lower Byte(I/O 1~8)
I/O1~I/O16 Data Inputs/Outputs DNU
Do Not Use
I/O1~I/O8
I/O9~I/O16
Data
cont
Data
cont
Data
cont
I/O Circuit
Column select
Column Addresses
/CS
/OE
/WE
Control Logic
/UB
/LB
CS2
2
Revision 0.2
Jul. 2010