FMP1617DAX Datasheet, PDF (1/11 Pages) FIDELIX – 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

FMP1617DAx
Document Title
1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
Revision History
Revision
No.
0.0
0.1
0.2
0.3
0.4
History
Initial Draft
Revised Load Condition
Revised I/O power (1.7V to VCC Æ 2.7V to VCC)
Revised VIH (VCC-0.4 Æ 0.8VCCQ)
Revised VIL (0.4 Æ 0.2VCCQ)
Revised ISB1 (110uA Æ 100uA)
Revised ISB0c (110uA Æ 100uA)
Revised ISB0b (100uA Æ 80uA)
Revised ISB0a (90uA Æ 70uA)
Correct typo in Array Refresh Area of Mode Register Set
Removed Page Write Operation
CMOS LPRAM
Draft date
Remark
Dec,08^th, 2008
Preliminary
Jul. 3^rd, 2009
Preliminary
Nov. 25^th, 2009
Preliminary
Feb. 3^rd, 2010
Jul. 21^st, 2010
Preliminary
Final
1
Revision 0.4
Jul. 2010