M21012_17 Datasheet, PDF (1/74 Pages) M/A-COM Technology Solutions, Inc. – Quad Multi-Rate CDR (42 Mbps - 3.2 Gbps)

M21011-12/M21012-12
Quad Multi-Rate CDR (42 Mbps - 3.2 Gbps)
Rev V4
Applications
• Backplane reach extension
• SONET OC-48, OC-48 with FEC systems and modules
• Fibre Channel systems
• Gigabit Ethernet systems
• 10GBASE-CX4 systems and modules
• Clock Synthesizer
Features
• M21012 has four independent Multi-Rate CDRs capable of running between 42
Mbps and 3.2 Gbps
• M21011 has four independent Multi-Rate CDRs capable of running between 1
Gbps and 3.2 Gbps
• Flexible DC-Coupled input interface to CML, LVPECL, and LVDS
• Flexible Control through I²C-compatible interface or hardwired pins
• Jitter generation 4.5 mUI rms, Jitter Tolerance 0.625 UI typical
• Signal conditioning features for superior performance on FR4 trace lengths of
up to 60", twinaxial cable lengths of up to 25m
• Typical Total Power Consumption as low as 400 mW with all channels running
• Built-in pattern generator and receiver for module and system testing
The M21012 is a high-performance quad multi-rate clock and data recovery (CDR) array, optimized for multi-lane telecom, and
datacom applications. Each channel has an independent multi-rate CDR capable of operating at data-rates between 42 Mbps
and 3.2 Gbps, allowing maximum flexibility in system design. The M21011 is rated for operation in the range of 1 Gbps to 3.2
Gbps. Aside from the difference in supported signal data-rates, the M21012 and M21011, are identical. Signal conditioning
features include input equalization and output pre-emphasis, allowing robust reception and transmission of signals to other
devices up to 60" away. User-selectable input interface types allow DC-coupled input to CML, LVDS, and LVPECL. The outputs
can also be DC-coupled to CML and LVDS. Frequency acquisition is accomplished with an external reference clock. The built-in
frequency synthesizer allows multi-rate operation, while operating with a single reference clock. The device can be controlled
either through hardwired pins or an I²C -compatible interface. The hardwired mode eliminates the need for an external micro-
controller, while allowing control of the key features of the device. The I²C-compatible interface allows complete control of the
device features.
Functional Block Diagram
Din0 [P/N]
Din1 [P/N]
Din2 [P/N]
Din3 [P/N]
Multifunction Pin Array
Serial Interface/Hardwired Mode
BIST Tx
Voltage
JTAG _Regulator
Cout0 [P/N]
Cout1 [P/N]
Cout2 [P/N]
Cout3 [P/N]
Dout0 [P/N]
Dout1 [P/N]
Dout2 [P/N]
Dout3 [P/N]
BIST Rx
1
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