FC3255 Datasheet, PDF (8/18 Pages) First Components International – 1.5A PWM Switching Regulators

FC3255 1.5A PWM Switching Regulators
Consequently, the current limit of the internal power
transistor current is reduced from its nominal value.
Switch Driver and Power Switch
The switch driver receives a control signal from the
logic section to drive the output power switch. The
switch is grounded through emitter resistors (63mW to-
tal) to the PGND pin. PGND is not connected to the
IC substrate so that switching noise can be isolated
from the analog ground. The peak switching current is
clamped by an internal circuit. The clamp current is
guaranteed to be greater than 1.5A and varies with
duty cycle due to slope compensation. The power
switch can withstand a maximum voltage of 40V on
the collector(V_SW pin). The saturation voltage of the
switch is typically less than 1V to minimize power dis-
sipation.
Short Circuit Condition
When a short circuit condition happens in a boost
circuit, the inductor current will increase during the
whole switching cycle, causing excessive current to
be drawn from the input power supply. Since control
ICs don's have the means to limit load current, an ex-
ternal current limit circuit(such as a fuse or relay) has
to be implemented to protect the load, power supply
and ICs.
In other topologies, the frequency shift built into the
IC prevents damage to the chip and external compo-
nents. This feature reduces the minimum duty cycle
and allows the transformer secondary to absorb ex-
cess energy before the switch turns back on.
3255 can be activated by either connecting the
V_CC pin to a voltage source or by enabling the SS pin.
When the V _CC voltage is below the minimum supply
voltage, the V_SW pin is in high impedance. Therefore,
current conduces directly from the input power source
to the output through the inductor and diode. Once
V_CC reaches approximately 1.5V, the internal power
switch briefly turns on. This is a part of nor-
mal operation. The turn-on of the power switch ac-
counts for the initial current swing.
When the V_C pin voltage rises above the threshold,
the internal power switch starts to switch and a volt-
age pulse can be seen at the V_SW pin. Detecting a
low output voltage at the FB pin, the built-in fre-
quency shift feature reduces the switching frequency
to a fraction of its nominal value, reducing the mini-
mum duty cycle, which is otherwise limited by the min-
imum on-time of the switch. The peak current during
this phase is clamped by the internal current limit.
When the FB pin voltage rises above 0.4V, the fre-
quency increases to its nominal value, and the peak
current begins to decrease as the output ap-
proaches the regulation voltage. The overshoot of
the output voltage is prevented by the active pull-on,
by which the sink current of the error amplifier is in-
creased once an overvoltage condition is detected.
The overvoltage condition is defined as when the FB
pin voltage is 50mV greater than the reference volt-
age.
COMPONENT SELECTION
Frequency Compensation
The goal of frequency compensation is to achieve
desirable transient response and DC regulation
while ensuring the stability of the system. A typical
compensation network, as shown in Figure 9, pro-
vides a frequency response of two poles and one
zero. This frequency response is further illustrated in
the Bode plot shown in Figure 9.
V_C
GM3255
GND
R1
C2
C1
Figure 9. A Typical Compensation Network
The high DC gain in Figure 10 is desirable for
achieving DC accuracy over ling and load variations.
The DC gain of a transconductance error amplifier
can be calculated as follows:
Where:
Gain_DC = G_M x R_O
G_M = error amplifier transconductance;
R_O = error amplifier output resistance 1MW
The low frequency pole, f_p1, is determined by the er-
ror amplifier output resistance and C1 as:
1
f_P1 =2_pC1RO
The first zero generated C1 and R1 is:
1
f_z1 = _2pC1R1