NM93C56A Datasheet, PDF (9/13 Pages) Fairchild Semiconductor – 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)

Timing Diagrams (Continued)
ERASE/WRITE DISABLE CYCLE (EWDS)
t_CS
CS
SK
DI
1 0 0 A_n A_n-1
A1 A0
Start Opcode
Address
Bit Bits(2)
Bits(8/9)
High - Z
DO
93C56A (ORG=1; A_n=A7):
Address bits pattern -> 0-0-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
93C56A (ORG=0; A_n=A8):
Address bits pattern -> 0-0-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
t_CS
CS
SK
DI
1 0 1 A_n A_n-1
A1 A0 D_n D_n-1
D1 D0
Start Opcode
Address
Data
Bit Bits(2)
Bits(8/9)
Bits(16/8)
High - Z
DO
93C56A (ORG=1; A_n=A7; D_n=D15):
Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0
(x -> Don't Care, can be 0 or 1; A6-to-A0 -> User defined)
Data bits pattern -> D15-to-D0; User defined
93C56A (ORG=0; A_n=A8; D_n=D7):
Address bits pattern -> x-A7-A6-A5-A4-A3-A2-A1-A0
(x -> Don't Care, can be 0 or 1; A7-to-A0 -> User defined)
Data bits pattern -> D7-to-D0; User defined
t_WP
Ready
Busy
WRITE ALL CYCLE (WRALL)
t_CS
CS
SK
DI
1 0 0 A_n A_n-1
A1 A0 D_n D_n-1
D1 D0
Start Opcode
Address
Data
Bit Bits(2)
Bits(8/9)
Bits(16/8)
High - Z
DO
93C56A (ORG=1; A_n=A7; D_n=D15):
Address bits pattern -> 0-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits pattern -> D15-to-D0; User defined
93C56A (ORG=0; A_n=A8; D_n=D7):
Address bits pattern -> 0-1-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits pattern -> D7-to-D0; User defined
t_WP
Ready
Busy
NM93C56A Rev. F.1
9
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