FPF2165R Datasheet, PDF (9/11 Pages) Fairchild Semiconductor – Full Function Load Switch with Adjustable Current Limit

Board Layout
For best performance, all traces should be as short as possible.
To be most effective, the input and output capacitors should be
placed close to the device to minimize the effects that parasitic
trace inductances may have on normal and short-circuit
operation. Using wide traces for V_IN, V_OUT and GND will help
minimize parasitic electrical effects along with minimizing the
case to ambient thermal impedance.
The middle pad (pin 7) should be connected to the GND plate of
PCB for improving thermal performance of the load switch. An
improper layout could result higher junction temperature and
triggering the thermal shutdown protection feature. This concern
applies when the switch is set at higher current limit value and
an overcurrent condition occurs. In this case power dissipation
of the switch (P_D = (V_IN - V_OUT) x I_LIM(max)) could exceed the
maximum absolute power dissipation of 1.2W.
FPF2165R Rev. A
9
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