FPF1013 Datasheet, PDF (9/11 Pages) Fairchild Semiconductor – IntelliMAX 1V Rated Advanced Load Management Products

Application Information
Input Capacitor
To limit the voltage drop on the input supply caused by
transient in-rush currents when the switch turns-on, a
capacitor must be placed between VIN and GND. For
minimized voltage drop, especially when the operating
voltage approaches 1V a 10μF ceramic capacitor should
be placed close to the VIN pins. Higher values of C_IN
can be used to further reduce the voltage drop during
higher current modes of operation.
Output Capacitor
A 0.1μF capacitor, C_L, should be placed between VOUT
and GND. This capacitor prevents parasitic board
inductance from forcing V_OUT below GND when the
switch turns off. If the application has a capacitive load,
the FPF1014 can be used to discharge that load through
an on-chip output discharge path.
Board Layout
For best performance, all traces should be as short as
possible. To be most effective, the input and output
capacitors should be placed close to the device to
minimize the effects that parasitic trace inductances
may have on normal and short-circuit operation. Using
wide traces or large copper planes for all pins (VIN,
VOUT, ON, and GND) helps minimize the parasitic
electrical effects along with minimizing the case-to-
ambient thermal impedance.
Figure 22. Proper Layout of Output, Input, and
Ground Copper Area
Demonstration Board Layout
FPF1013/4 demonstration board has the components
and circuitry to demonstrate the load switches functions.
Thermal performance is improved using techniques
recommended in the layout recommendations section of
datasheet.
Improving Thermal Performance
Improper layout can result in higher junction
temperature. This applies when continuous operation
current is set to maximum allowed current and switch
turns into a large capacitive load that introduces high
inrush current in the transient. Since FPF1013/14 does
not have thermal shutdown feature, proper layout can
essentially reduce power dissipation of the switch in
transient and prevents the switch exceeding the
maximum absolute power dissipation of 1.2W.
The VIN, VOUT, and GND pins dissipate most of the
heat generated during a high load current condition. The
layout suggested in Figure 22 provides each pin with
adequate copper so that heat may be transferred as
efficiently as possible out of the device. The ON pin
trace may be laid out diagonally from the device to
maximize the area available to the ground pad. Placing
the input and output capacitors as close to the device as
possible also contributes to heat dissipation, particularly
during high load currents.
Figure 23. Demonstration Board Layout
© 2009 Fairchild Semiconductor Corporation
FPF1013 / FPF1014 • Rev. 1.0.8
9
www.fairchildsemi.com