FMS6501_06 Datasheet, PDF (9/14 Pages) Fairchild Semiconductor – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

Acknowledge
The data bytes transferred between the START and
STOP conditions from transmitter to receiver is unlim-
ited. Each byte of eight bits is followed by an acknowl-
edge bit. The acknowledge bit is a high-level signal put
on the bus by the transmitter, during which the master
generates an extra acknowledge-related clock pulse. A
slave receiver must generate an acknowledge after the
reception of each byte. A master receiver must generate
an acknowledge after the reception of each byte that has
been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse so the SDA line
is stable LOW during the HIGH period of the acknowl-
edge-related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte clocked out of the slave. In
this event, the transmitter must leave the data line HIGH
to enable the master to generate a STOP condition.
START
condition
SCL FROM
MASTER
1
2
clock pulse for
acknowledgement
8
9
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
Figure 6. Acknowledgement on the I²C Bus
I²C Bus Protocol
Before any data is transmitted on the I²C bus, the device
that should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I²C bus configuration for a data
write to the FMS6501 is shown in Figure 5.
1
91
9
SCL
SDA
START BY
MASTER
A6 A5 A4 A3 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
FRAME1
SERIAL BUS ADDRESS BYTE
ACK. BY
FMS6501
FRAME 2
ACK. BY
FMS6501
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
ACK. BY _{STOP BY}
FMS6501 _MASTER
Figure 7. Write a Register Address to the Pointer Register, Then Write Data to the Selected Register
© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.2
9
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