FDMF8704V Datasheet, PDF (9/11 Pages) Fairchild Semiconductor – High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator

Module Power Loss Measurement and
Calculation
Refer to Figure 18 for module power loss testing method. Power
loss calculation are as follows:
(a) P_IN
(b) P_OUT
(c) P_LOSS
= (V_IN x I_IN) + (V_CIN x I_CIN) (W)
= V_O x I_OUT (W)
= P_IN - P_OUT (W)
PCB Layout Guideline
Figure 19. shows a proper layout example of FDMF8704V and
critical parts. All of high current flow path, such as V_IN, VSWH,
V_OUT and GND copper, should be short and wide for better and
stable current flow, heat radiation and system performance.
Following is a guideline which the PCB designer should
consider:
1. Input bypass capacitors should be close to V_IN and GND pin
of FDMF8704V to help reduce input current ripple component
induced by switching operation.
I_IN
V_IN
A
C_VIN
2. It is critical that the VSWH copper has minimum area for
lower switching noise emission. VSWH copper trace should
also be wide enough for high current flow. Other signal routing
path, such as PWM IN and BOOT signal, should be considered
with care to avoid noise pickup from VSWH copper area.
3. Output inductor location should be as close as possible to the
FDMF8704V for lower power loss due to copper trace.
4. Snubber for suppressing ringing and spiking of VSWH
voltage should be placed near the FDMF8704V. The resistor
and capacitor need to be of proper size for power dissipation.
5. Place boot diode, ceramic bypass capacitor and boot
capacitor as close to V_CIN and BOOT pin of FDMF8704V in
order to supply stable power. Routing width and length should
also be considered
6. Use multiple Vias on each copper area to interconnect each
top, inner and bottom layer to help smooth current flow and heat
conduction. Vias should be relatively large and of reasonable
inductance.
I_CIN
A
C_CIN
V_CIN
DISB
PWM
Input
VIN VCIN
DISB
BOOT
HSEN
PWM
VSWH
CGND PGND
C_BOOT
V V_O
I_OUT
A
C_OUT
OUTPUT
Figure 18. Power Loss Measurement Block Diagram
FDMF8704V Rev. G
Figure 19. Typical PCB Layout Example (Top View)
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